La DAQ pour les projets ANR et EUDET Remi Cornat, Julie Prast Pour la collaboration SOCLE – 19 Novembre 2007.

Présentation au sujet: "La DAQ pour les projets ANR et EUDET Remi Cornat, Julie Prast Pour la collaboration SOCLE – 19 Novembre 2007."— Transcription de la présentation:

1 La DAQ pour les projets ANR et EUDET Remi Cornat, Julie Prast Pour la collaboration SOCLE – 19 Novembre 2007

2 2 Plan Architecture de la DAQ finale La carte DIF pour DHCAL (ANR) La carte DIF pour ECAL (EUDET) La DIF Task Force

3 3 Final DAQ architecture Slab hosts VFE chips DIF connected to Slab LDA servicing DIFs LDAs read out by ODR PC hosts ODR, through PCIe C&C routes clock, controls0 DIF: Detector InterFace LDA: Link/Data Aggregator ODR: Off-Detector Receiver C&C: Clock & Controls PCIe: PCI-Express From Bart Hommels, University of Cambridge, Eudet 07

4 4 ODR and LDA ODR is a commercial FPGA board with high speed serial interfaces and a PCIe host bus (Virtex4-FX100, PCIe 8x, etc.) Customised firm- and software: DMA driver pulls data off the onboard RAM, writes to disk Performance studies & optimisation ongoing 1 st Prototype is (also) a commercial FPGA board with customised firmware and hardware add- ons: –High-bandwidth link to ODR –Many links towards DIFs ODR is the interface between DAQ and the ‘PC-world’ LDA interfaces many DIFs with few high-speed links From Bart Hommels, University of Cambridge, Eudet 07

5 5 DIF Functionality Receive, regenerate and distribute clocks Receive, buffer, package and send data from VFE to LDA Receive and decode incoming commands and assert corresponding signals Receive, decode and store block transfers Control power pulsing and provide watchdog functionality Control the DIF-DIF redundancy connection Provide an USB interface for stand-alone running and debugging …..on top of that: all the things we did not think so far From Bart Hommels, University of Cambridge, Eudet 07

6 6 The DHCAL board prototype 4 HaRDROC chainés pour minimiser le nb de fils sur le détecteur DIF FPGA HR Clock + config+ control Data DIF FPGA USB DAQ analogique SLAB Analog Carte reçue en juin dernier (LAL, LLR, IPNL). Test des HaRDROC OK (LAL). Code FPGA et soft PC en cours de finalisation (LLR, IPNL). ADCADC

7 7 La DIF pour DHCAL au m 2 Séparée des Slabs pour plus de souplesse. Gere les slabs  nb HardROC (WR config + RD data). Compatible avec la DIF Task Force et la DAQ finale. –Interface LDA vers la DAQ finale –Interface USB pour le debug et tests standalone. –Interface DIF DIF Sortie analogique conservée pour le debug et les tests en faisceau. Orientée basse conso (power pulsing, no clk pendant interbunch, …) Inclue le slow control. FPGA ASIC Config ASIC read DAQ interface Slow control Power Supplies DIF LDA (HDMI) DAQ0 (SCSI) USB SLABSLAB JTAG HardRoc analog output

8 8 La DIF pour DHCAL au m 2 (2) Fin 07: –Choix taille des ASUs –Interconnexion des ASUs –Schéma fonctionnel de la DIF –Finalisation Interface DIF / SLAB Mai 08 : 1 DIF et 1 SLAB fabriqués. Fin juin 08 : DIF + SLAB testés. Sept 08 : Ensemble des DIFs et des slabs dispo pour le m 2. Responsabilité : LAPP, IPNL, LLR, LAL. Schéma non contractuel : taille des ASUs à definir !

9 9 Module ECAL for EUDET ASU DIF Connexion ? Layout ? SLAB : –1 termination cap –7 standard ASUs (Active Sensor Unit) 18.5 x 18.5 cm2 4 wafers of 18x18 pixels 4 SKIROC chips per wafer (81 channels each) –1 termination ASU variable length according to the layer 15 layers –1 DIF ASU Concept : to be the most representative of the final detector module –15 Detector slabs with FE chips integrated - 1 long and complete slab (L=1.5m) - 14 short slabs to obtain a complete tower of detection (typ. L=30 cm?) and design of compact outlet. Courtesy of Marc Anduze (LLR) From Remi Cornat, LPC

10 10 The expected alveolar thickness is 6.5 mm Heat shield: 100+400 µm (copper) Design EUDET Slab PCB: 800 µm glue: <100 µm (needs tests) wafer: 320 µm Chip without packaging Kapton ® film: 100 µm 6000 µm Mechanical constraints for the DIF Chips and bonded wires inside the PCB Very thin space is allowed for DIF components 50 mm x 80 mm x ~6 mm (final) X mm x 180-80 mm x Z mm (EUDET relaxed constraints/options) Courtesy of Marc Anduze (LLR) From Remi Cornat, LPC

11 11 ASU edge connector 18.5 cm ASU will be glued edge to edge Glue provides electrical contact Glue dot diameter reach 2 mm allowing a maximum number of contacts of about 3/cm. Old design Discussions for optimization, reliability, … are ongoing : a list of signal and some electrical specifications have been discussed From Remi Cornat, LPC

12 12 Conclusion for ECAL DIF Stringent mechanicals constraints about DIF design Choices should be done to remains close to what a final version could be LPC is involved in the DIF task force First step to list SLAB-DIF interface signals and optimisation : done ! DIF specifications document at system level by the end of this year General purpose DIF prototype under design at LPC pcb place&route to be done soon Includes 1 FPGA, USB, 1 10b ADC, NIM I/O and connectors Mezzanines boards according to application Test of SKIROC’08 (Q3’08) Cosmic test of ASU (Q4’08) From Remi Cornat, LPC

13 13 DIF Task Force Many similarities between the 3 subdetector ASICs (SPIROC, SKIROC, HARDROC) and between the 3 DIFs (ECAL, AHCAL, DHCAL). To avoid duplication (triplication) of work, a small working group of 4 people has been created : –Remi Cornat (Clermont) : ECAL –Mathias Reinecke (DESY) : AHCAL –Julie Prast (Annecy) : DHCAL –Bart Hommels (Cambridge) : DAQ Aim of the task force : –Define the interface between SLABs and DIF (connector pinout, electrical signals and levels, …) –Define the DIF architecture : common blocks and detector specific blocks, interface to DAQ and USB. –Define the slab to slab interface. –Define common VHDL libraries. –Summarize everything in a common document for the end of this year.

14 14 Conclusion De nombreux progrès ont été réalisés sur l’acquisition –DAQ « finale » coté anglais. –DIF pour ECAL (EUDET) –DIF pour DHCAL (ANR) Un groupe de travail a été mis en place « la DIF Task force » et a déjà montré son efficacité. Les efforts convergent maintenant vers la réalisation de proto technologiques de plus grande taille pour montrer la faisabilité (cout + industrialisation) du détecteur.