3D LHC 29 November 2007 A.Rozanov

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Transcription de la présentation:

3D LHC 29 November 2007 A.Rozanov Introduction Objectif minimale : repeter FE-I4-Proto avec a)5+1 niveaux de metal b) vias en wire-bond Objectif principal: version 3D de FE-I4-Proto avec tier analogique et tier digital Objectif federateur: test chip avec daisy chains of vias and contacts, transisteurs aux differend distances Responsible ? 3D LHC 29 November 2007 A.Rozanov

Capacitance Measurement ShuLDO+trist LVDS/LDO/10b-DAC FE-I4_proto1 FE-I4-P1 3mm Participating institutes: Bonn, CPPM, Genova, LBNL, Nikhef. LDO Regulator 61x14 array Control Block Charge Pump Capacitance Measurement SEU test IC 4mm DACs Current Reference ShuLDO+trist LVDS/LDO/10b-DAC 4-LVDS Rx/Tx

Analog tier In FE-I4_proto1 50 mm 145 mm discri TDAC Preamp FDAC Config Logic 145 mm

Digital Readout Architecture FE-I3 Both FE readout based on double column (DC) structure FE-I4 bottleneck local storage low traffic on DC bus All hit pixels are shipped to EoC buffer. A hit pixel need to transfer its data to EoC before accepting new hit  congestion. Each pixel is logically independent inside the DC. Store data locally in DC until L1T. Only 0.25% of pixel hits are shipped to EoC  DC bus traffic “low”. Warning: Local Buffer Congestion??? Each pixel is tied to its neighbors -time info- (clustered nature of real hits).

3D LHC 29 November 2007 A.Rozanov Details Utiliser (ou non) les couches bonding pour les bus Vdd /Vdda ? Multiplicite des points de bonding: Fe-I4 a naturellement 4 types de pixels, donc motif de (12+1+12)x(62+1+62)=2*50 um x 2*125 um Passage de tier1 a tiers2 via les bus lines s’ils ne sont pas dans chaque pixel ? 3D LHC 29 November 2007 A.Rozanov