Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 A 65nm CMOS Fully Integrated 31.5dBm Triple SFDS Power Amplifier dedicated to W CDMA Application Y. Luque 1, N. Deltimple 1, E. Kerherve 1, D. Belot 2 1 IMS Laboratory, University of Bordeaux, IPB/ENSEIRB-MATMECA, IMS laboratory, Talence cedex, Fance 2 STMicroelectronics, Minatec, Grenoble, France

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Outline Introduction –Context –State of the art –Targeted standard Triple Stacked Folded pseudo-Differential Structure (SFDS) PA –Triple SFDS circuit –Triple SFDS behavior 65 nm CMOS Triple SFDS PA –Overall PA –CW simulation –HPSK simulation Conclusion and future works

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Outline Introduction –Context –State of the art –Targeted standard Triple Stacked Folded pseudo-Differential Structure (SFDS) PA –Triple SFDS circuit –Triple SFDS behavior 65 nm CMOS Triple SFDS PA –Overall PA –CW simulation –HPSK simulation Conclusion and future works

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Telecommunication market Increase the interactive services in mobile phones while limiting the fabrication cost and the phone size. –Reduce die area of circuits in order to implement new services –Reduce the cost of each chip –To level the eventual disappearance of old CMOS technologies WWAN WMAN WLAN WPAN GSM (2G) EDGE (2.5G) UMTS (3G) HSPA (3.5G) LTE (4G) WiFi GPS Bluetooth Zigbee WiMAX, UWB MBWA Proposition : Design a PA using 65 nm CMOS technology dedicated to UMTS standard

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 UMTS (3G) UMTS (Universal Mobile Telecommunication System) –P out(max) = 24 dBm (the most widespread) –Freq = GHz Tx (2Mbps) –Modulation schemes (QPSK, HPSK) High output power for long distance communication with 65 nm CMOS technology Power challenge

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 W-CDMA W-CDMA (Wideband Code Division Multiple Access) –HPSK Modulation (Hybrid Phase-Shift Keying) non constant modulation envelope –Requirement on Pout From -20dBm to 24dBm –Requirements on linearity : ACPR 1 =-33dBc at +/- 5MHz ACPR 2 =-43dBc at +/- 10MHz HD3<40dBc Linearity challenge optimize the linearity-efficiency trade-off use a structure allowing to high gain to avoid a third stage (linearity-gain trade-off)

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS nm CMOS technology 65 nm 130 nm 130 nm MW 250 nm Low backend More resistive Reduction of back-end leads to: - decrease the quality factor of passive devices - increase electro-migration matters - increase capacitive parasitic and resistive issues - RF signal losses through the bulk BiCMOS backend CMOS backend

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 RefCMOS (nm) Pout (dBm) Gain (dB) PAE (%)structure *[FRI08] 65 (B VDS =3.3V) Max: NC OCP1: 19,6 18 Max: OCP1: 5,8 Diff Cascode *[WAN08] 65 (B VDS =6.2V) Max: 27 OCP1: 25,3 35 Max: OCP1: 10 Diff Cascode (self- biased) [AFS10]65 Max:31,5 OCP1: 27,5 32 Max: OCP1: Diff Cascode PA + DAT (Two stages) with PPA 65 nm CMOS PA state of the art high B VDS transistors Distributed Active Transformer (DAT) High die area Process option (cost) Proposition : Design of elementary topology with low B VDS transistors and without DAT

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Outline Introduction –Context –State of the art –Targeted standard Triple Stacked Folded pseudo-Differential Structure (SFDS) PA –Triple SFDS circuit –Triple SFDS behavior 65 nm CMOS Triple SFDS PA –Overall PA –CW simulation –HPSK simulation Conclusion and future works

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Triple SFDS overview Triple SFDS schematic Input Output VDS M1 VDS M2 VDS M3 Small signal equivalent circuit

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 SFDS increases simultaneously the OCP1, the PAE and the Pmax SFDS versus differential 1,95 GHzSFDSDiff cascode P max 30.7 dBm29.2 dBm OCP128 dBm24 dBm PAE max 33 %31 % PAE OCP1 21 %10 % Gain14.8 dB15.2dB SFDS Diff cascode

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Outline Introduction –Context –State of the art –Targeted standard Triple Stacked Folded pseudo-Differential Structure (SFDS) PA –Triple SFDS circuit –Triple SFDS behavior 65 nm CMOS Triple SFDS PA –Overall PA –CW simulation –HPSK simulation Conclusion and future works

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Overall PA Triple SFDS Differential Cascode - Gain Differential Cascode Triple SFDS - Linearity, power Requirements: - OCP 1 = 27 dBm to be linear until 24dBm (back-off = 3dB) - B VDS = 1.8V Matching

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 CW simulation 1.95 GHz S dB S dB S dB S GHz Pout (max) 31.5 dBm OCP dBm PAE (max) 19.5 % 10 % B W_ 3dB = 25%

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 ACLR respected until 23 dBm with an EVM of 5% HPSK simulation results HSPK simulation with ADS analogRF ACLR 1 results according to P out Constelation

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 RefCMOS (nm) Freq (GHz) Vsupply (V) Pout (dBm) Gain (dB) PAE (%)Standardstructure FOM - ITRS (W.GHz²) [SEO06] RFIC Max: 23 OCP1: Max: OCP1: 30,2 NCTriple cascode32 [REY07] JSSC Max: 23 OCP1: NC 15 Max: OCP1: NC BluetoothPAs+DAT13 [LIU08] JSSC Max: 27 OCP1: 24 NC Max: OCP1: 25 NCDiff PAs + DAT37 [HAL07] RFIC Max: 24,3 OCP1: Max: OCP1: 15 NCDiff PAs +DAT16 [CHO09] ISSCC Max: 30 OCP1: Max: OCP1: 23 WiMAX Diff Cascode PA + DAT (Two stage) 1101 *[FRI08] EuMC08 65 (BVDS=3.3V) Max: NC OCP1: Max: OCP1: nDiff CascodeNC *[WAN08] ESSCIRC08 65 (BVDS=6.2V) Max: 27 OCP1: Max: OCP1: 10 NC Diff Cascode (self-biased) 1280 [AFS10] ISSCC Max:31.5 OCP1: Max: OCP1: 19 WLAN Diff Cascode PA + DAT (Two stage) with PPA 3359 This work Max:31,5 OCP1: 27,5 35 Max: OCP1: 10 UMTSTriple SFDS3312 Comparative table Without DAT With DAT * High BVDS transistors [FRI08]-3.3V [WAN08]-6.2V

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Outline Introduction –Context –State of the art –Targeted standard Triple Stacked Folded pseudo-Differential Structure (SFDS) PA –Triple SFDS circuit –Triple SFDS behavior 65 nm CMOS Triple SFDS PA –Overall PA –CW simulation –HPSK simulation Conclusion and future works

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Conclusion Challenge to design a CMOS PA dedicated to UMTS application. Demonstration of a simulated PA constrained by stringent restrictions on low B VDS active device. Validation of a new topology using low B VDS transistors & without DAT. Achievement of a Pmax= 31.5dBm OCP1=27.5dBm at 1.9GHz with simulated 65nm CMOS technology provided by STMicrolectronics DK. ACLR is respected until 23 dBm (EVM=10%) Efficiency enhancement technique (dynamic biasing) Layout achievement and measurements Future works

Laboratoire de lIntégration du Matériau au Système CNRS UMR ICECS 2010 Thanks for your attention