E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT La Nanoélectronique et la mécanique quantique font-elles bon ménage ? Simon Deleonibus Laboratoire Nanodispositifs Electroniques (Electronic Nanodevices Laboratory) CEA/LETI/Département NANOTEC(NANOTEC Division)  CEA Grenoble 17 rue des Martyrs 38054 Grenoble Cedex France Tel : 33 (0)4 38 78 59 73 Fax: 33 (0)4 38 78 54 59 email: sdeleonibus@cea.fr E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT course à l’intégration / course à la miniaturisation loi de Moore initiale (1965) : nbr. transistors x 2 /an DRAM X4/3ans Convergence MPU X2.5/3ans Internet Portable Camera Digitale Dimension critique 4004 8080 8086 80286 i386 i486 Pentium Pentium II Pentium III Pentium IV Itanium 1k 4k 16k 64k 256k 1M 4M 16M 64M 128M 256M 512M 1G 2G 4G 1 milliard Home PC Introduction ULK (11niv met) Office PC microprocesseurs Introduction polymères +ALD (10niv met) 10 millions mémoires dynamiques (DRAM) Introduction Cu+H(M)SQ (9niv met) Main Frame VCR Defense Introduction Cu (7niv met) Introduction FSG(6 niv met) Introduction damascene(5niv met) Introduction vias « plugs »,CMP(4niv met) Introduction STI, salicide C.T.V. Introduction contacts « plugs »(3niv met) Introduction polycide Introduction poly gate Progrès possible grâce à l’introduction continue d’innovations E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Three major product families Nomadic consumer and professional products: biggest market share Three major product families few 109 tr./system High Performance (HP) t=CV/I Connection to power network Low Operating Power (LOP) Intermittent Nomadic Function Low Stand-by Power (LSTP) Pstat= VddxIoff Permanent Nomadic Function 109 tr./system few 108 tr./system Pdyn=CVdd2 f Ptot=Pstat+ Pdyn E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT La baisse des coûts, moteur de la diffusion de la microélectronique Une réduction des coûts unique dans l’histoire de l’industrie (500 000 F) Coût de 1 million de transistors (équivalent à un livre de 200 pages) (40 000 F) (3 000 F) (800 F) (200 F) (35 F) (3 F) (40 centimes) (3 centimes) 1973 1977 1981 1984 1987 1990 1995 2000 2005 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Les deux secrets de la microélectronique De plus en plus de transistors par centimètre carré de Silicium Miniaturisation 1 lot de fabrication à ST Crolles 2 : = 500 milliards de transistors !!! En 2015, l’ensemble des livres de la BNF F. Mitterrand sur une seule puce de silicium ! De plus en plus de centimètres carrés de Silicium traités simultanément Traitement collectif Réduction des coûts Plaques de silicium de 100, 200, puis 300 mm de diamètre Lot de fabrication E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT 1999: First 20nm MOSFET Beyond the roadmap !! Estimated metallurgical length: 4 nm(1018cm-3) source gate extension drain HDD pockets Lm Lg Gate oxide SiO² hard-mask Simulation (ATHENA/SILVACOTM) 20nm poly-gate MOSFET (hybrid lithography) 1.2nm gate oxyde Gate length: 20nm Gate oxide thickness:1.2nm Extensions; BF2 pockets; n+ HDD S.Deleonibus et al. ED Letters April 2000 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Nanoscale bulk MOSFET Lg= 15nm Leakage currents and Access resistance are still issues source gate extension drain HDD pockets Lm Lg Gate oxide Scattering by impurities of highly doped short channel ( room temperature) Low field mobility degradation due to halo overlap mostly in the case of efficient SCE control LETI: G. Bertrand et al., ULIS 2003, SSE 2004 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Sommaire Introduction et contexte Dispositifs CMOS : physique, effets ultimes (géometries ultimes) Feuille de route de la nanoélectronique et mise à l’échelle linéaire (ITRS and linear down scaling) Nécessaires « Boosters » pour maintenir le progrès Nouveaux matériaux pour amélioration CMOS: transport, parasites et courant de fuite Nouvelles architectures CMOS Nanoélectronique Architectures post CMOS. Opportunités mémoires Conclusions : futurs systèmes/puce(SOC), feuille de route E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Sommaire Introduction et contexte Dispositifs CMOS : physique, effets ultimes (géometries ultimes) Feuille de route de la nanoélectronique et mise à l’échelle linéaire (ITRS and linear down scaling) Nécessaires « Boosters » pour maintenir le progrès Nouveaux matériaux pour amélioration CMOS: transport, parasites et courant de fuite Nouvelles architectures CMOS Nanoélectronique Architectures post CMOS. Opportunités mémoires Conclusions : futurs systèmes/puce(SOC), feuille de route E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Transistor MOS isolant de grille Lg grille Tox extension source Xj drain HDD L n(p) p(n) n(p) Canal substrat Courant d’inversion faible (« sous le seuil ») Courant de saturation (inversion forte) Tension de seuil E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Saturation regime and non equilibrium Velocity saturation : vsat max ≤vth where: Velocity overshoot : vinj>vsat Non equilibrium (non stationary transport). If no collision in channel : ballistic transport E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Classical parasitic effects oVg oVs(0V) oVd gate current DIBL substrate current punch through SCE SCE : Short channel effect (charge sharing S-D-G) Effet de canal court(perte de contrôle charge) DIBL: Drain Induced barrier Lowering Abaissement de barrière induit par le drain E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Caractéristiques et effets parasites dans un transistor MOS « Courant de saturation » Sous le seuil Lg = 75 nm Lg = 65 nm Vg step = 250 mV W = 10 µm VT VT: tension de seuil DIBL(*) perçage inversion forte inversion faible(pente 1/S) DVT=DIBL+SCE SCE(*) 65nm 75nm

Parasitic effects in an ultimate MOSFET oVg oVd Direct tunneling gate current DIBL Field assisted tunneling current Punch-through SCE S-D direct tunneling Tox U0 * DIBL+SCE + punch-through : classical effects * Direct tunneling current through gate oxide * Field assisted tunneling current drain/channel diode - E I~ F2exp[-A Eg 3/2 / F] * direct tunneling current between source and drain(<10nm) E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Sommaire Introduction et contexte Dispositifs CMOS : physique, effets ultimes (géometries ultimes) Feuille de route de la nanoélectronique et mise à l’échelle linéaire (ITRS and linear down scaling) Nécessaires « Boosters » pour maintenir le progrès Nouveaux matériaux pour amélioration CMOS: transport, parasites et courant de fuite Nouvelles architectures CMOS Nanoélectronique Architectures post CMOS. Opportunités mémoires Conclusions : futurs systèmes/puce(SOC), feuille de route E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

ITRS: 3 devices families according to applications MOSFET Engineering ITRS: 3 devices families according to applications Isat, Vdd vs Ioff ITRS 2003 500 1000 1500 2000 2500 3000 0,001 0,01 0,1 1 10 100 Ioff(nA/µm) Isat(µA/µm) 0,2 0,4 0,6 0,8 1,2 1,4 VDD(V) LOP HP LSTP Low STandby Power Low Operating Power High Performance 18 110 22 32 45 65 80 90 td = CV/Isat Ptot= Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd2 f

Classical MOSFET linear scaling Channel length K Voltage U Gate oxide K Junction depth K Electric field U/K2 Channel doping U/K Parasitic capacitance K(ACox,ACj) Current (vel. sat.) U2/K(U) Delay(vel. sat.) K2/U(K) Power (vel. sat.) U3/K(U2) Speed.Power product KU2 To double density (X2), (follow Moore’s law) then Nowadays ITRS trend from technology node to the next node !! i.e. Node n: D Node n+1: K.D Baccarani et al,IEDM 1984

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Sommaire Introduction et contexte Dispositifs CMOS : physique, effets ultimes (géometries ultimes) Feuille de route de la nanoélectronique et mise à l’échelle linéaire (ITRS and linear down scaling) Nécessaires « Boosters » pour maintenir le progrès Nouveaux matériaux pour amélioration CMOS: transport, parasites et courant de fuite Nouvelles architectures CMOS Nanoélectronique Architectures post CMOS. Opportunités mémoires Conclusions : futurs systèmes/puce(SOC), feuille de route E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Basic Quantum effects on energy Schroedinger’s equation: Possible solutions: Eigenvalues for energy E and eigenfunctions (E, k - allowed values in reciprocal space) Typical significant cases in Microelectronics Potential well : Standing waves L U0 Energy Barrier: tunneling Coupling with Poisson equation: « quantum correction »=> Electric field=> motion Coupling with Boltzmann’s equation: hydrodynamic particle flow (current) and combination of both: inversion layer at MOS gate oxide interface! Tb E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Coexistence of 3D and 2D electron gases Coexistence of 3D and 2D electron gases at a MOSFET interface 2D electron gas energy splitting in triangular potential « Dead depleted » zone  quantum correction quantum correction 3D gas continuum EF 2D gas discretized levels M O S Quantum confinement => degeneracy splitting (id. standing waves) repopulation of higher energy levels with different meff higher threshold energies required « dead depleted » zone due to reflexion of electron wave function E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Example: Global Strain on Si/SiGe Ev Ec D (2) (4) hh lh Si x Ge 1 - =0.6x Ec Ev lh hh D (4) (2) Si x Ge 1 - =0.74x Band offset and splitting Lower meff bands accessible E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Strain and bandgap engineering Global Compressive Compressive strain strain Tensile strain Tensile strain Tensile strain Tensile strain Si x Ge 1 - a= 5.43 5.43<a<5.65 a= 5.43 pMOS Si Si x Ge 1 - Si 1 - y C Si x Ge 1 - Si Ge Si Si C C Si Si x 1 - x 1 1 - - y y y y Si Si Si Si Ge Ge x x 1 1 - - x x Band offset and splitting Ec Ev lh hh D (4) (2) Si x Ge 1 - =0.74x hh lh y C = 6.5y =0.6x Band Band offset offset and splitting and splitting 5.43<a<5.65 Stressors (CESL, source & drain, salicide,…) In Si In Si Ge Ge C C No No strain strain if x=10y if x=10y 1 1 - - x x - - y y x x y y nMOS pMOS Local E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Strained Si + strained Ge channels Improved hole mobility in compressively strained Ge and electron mobility in tensely strained Si Symetrical drain current for any dual channel CMOS LETI: Weber et al., IEDM, 2005 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Short channel issues on strained architectures Global + Local Global LETI: F.Andrieu et al. VLSI Tech. Symp, June 2005,Kyoto E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Ultimate transport properties in Si. Ballistic effects <v(n)> average thermal velocity Ceff gate/channel capacitance T: transmittance Lg< Lm(mean free path 100nm@300K) Ballistic and Diffusive Transport Thermionic current Tunneling current Initial injection velocity at source Reflexion on ionized dopants(channel or drain) Interface roughness Backscattering at the source , from dopants will reduce ballisticity S.Datta etal, IEDM 1998, San Francisco(CA) Dec 1998 G.Bertrand et al SNW2000 Honolulu(HI), ULIS2003Munchen(FRG) E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Scaling supply voltage P = Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd2 f Issues to address(trade of Performance & Power): room temperature operation threshold voltage control parasitic effects The most severe constraints are due to(*) : doping concentration fluctuations small volume,asymetry short channel effects low DVT vs. VT - low Vsupply - Tox thickness,doping concentration, Xj leakage current in subthreshold regime even with S=60mV/dec(FDSOI) and VT = 0,20V (Vsupply=0,5V) we will get Ioff = 1nA/µm tunnel currents SiO2 tunneling dielectric , F-N high doping level (*) much higher impact than thermal fluctuation, energy equipartition, quantum fluctuations S.Deleonibus et al. ESSDERC 1999, Leuven, Sept 1999 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

High K dielectric integration:Replacing SiO2 Tox=1.2nm Active area(10cm2 circuit): 1cm2 *Pstat(0.5V)= 5W => 500W/m2(1/2 AM1) *Pstat(1V) = 50W => 5kW/m2 *Pstat(1.5V) = 750W !! => 75kW/m2!! (Small Nuclear Power station to keep 50 000 PC in standby mode!! …) SixOxN y or large mobility gap Si High K material Gate (poly,metal) (*) SiO2 AlN Al2O3 Si3N4 Ta2O5 TiO2 BaTiO3 HfO2 ZrO2 Ec(MV/cm) 10 - 13 6 15 5 3. 1 3 ε r 9 8. 7. 22 27 40 60 100 >1000 30 25 Eg(eV) 6. 2 7 8 4. 4 4.3 5.68 5.16 7.8 Bulk materials characteristics Possible candidates E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Metal Workfunctions Fm « Dead depleted » zone reduce gate depletion capacitance Vacuum level Nb 3.99-4.30 Al 4.06-4.20 Ta 4.12-4.25 Mo 4.30-4.60 Zr 3.90-4.05 V 4.12-4.30 Ti 3.95-4.33 TaN 4.2-3.9 qSi= 4.05eV Ec mn+(Ei+0.55V) Silicon mn(Ei+0.2V) ZrSi2 TiSi2 TaSi2 CrSi2 MoSi2WSi2 NiSi2CoSi2 RhSi PdSi TaSixNy WSixNy WCxNy TiSixNy Co 4.41-5.00 Ru 4.60-4.71 W 4.10-5.20 Rh 4.75-4.98 Os 4.70-4.83 Au 4.52-4.77 Cr 4.50-4.60 Pd 4.80-5.22 Ei Midgap Eg=1.12eV WNx TiNx 4.60-4.90 qmSi(Ei)=4.61eV mp(Ei-0.2V) Re 4.72-5.00 Ir 5.00-5.70 Pt 5.32-5.50 RuO2 4.90-5.20 mp+(Ei-0.55V) Ev SMSze Physics of Semiconductor Devices 1981 J.Hauser IEDM 1999 Short Course E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Sommaire Introduction et contexte Dispositifs CMOS : physique, effets ultimes (géometries ultimes) Feuille de route de la nanoélectronique et mise à l’échelle linéaire (ITRS and linear down scaling) Nécessaires « Boosters » pour maintenir le progrès Nouveaux matériaux pour amélioration CMOS: transport, parasites et courant de fuite Nouvelles architectures CMOS Nanoélectronique Architectures post CMOS. Opportunités mémoires Conclusions : futurs systèmes/puce(SOC), feuille de route E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT SiO2 Si tSi L Silicon On Insulator M. Bruel, Elec. Lett., vol. 31, n° 14, p. 1201, 1995 A B Initial silicon Oxidation Smart - Cut implant Cleaning and bonding Buried oxide H + ions 5.10 16 cm 2 Smart-Cut process Cj -reduced parasitic capacitance -improved isolation -improved electrostatics improved FOM /bulk E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Co-integrated Dual Strained Channel On Insulator 20nm sSDOI nFETs LTiN=14 nm 20nm pFETs LTiN=12nm BOX Si0.6Ge0.4 sSDOI NiSi Poly Si TiN HfO2 down to 12nm gate length with a high-k/metal gate stack VT matching SOI -> LP DCOI -> HP F. Andrieu et al., IEEE SOI conf., 2005 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Fully Depleted SOI VT(V) Tsi(nm) Bulk or PD SOI like FDSOI Quantum confinement N+ poly gate Fully depleted SOI: Quantum confinement in thin film(TSi thk): Low Doped thin channel => Lower dopant fluctuations => Higher VT stability vs thickness Gate Workfunction engineering for dual gate /undoped FD channel Low VDD J.Lolivier et al, ECS Spring meeting, Paris, May 2003 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Planar or non planar? (design/layout issue very strong) FDSOI optimization from single gate to multi gate PLANAR DGMOS Planar or non planar? (design/layout issue very strong) BOX GATE CHANNEL FINFET, Tri Gate WFET With thinner buried oxide , fringing fields in substrate depletion region GATE SOURCE DRAIN SILICON SUBSTRATE Fringing fields through buried oxide contribute to SCE Adding a ground - plane help reducing SCE and DIBL but degrade Ssw Except if plane connected to gate => Double gate device 1 2 3 4 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Double gate - channel population Ravaioli, SINANO Modeling Summer School Glasgow Aug 2005 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Double gate versus Single gate(FDSOI) MOSFET by Wafer Bonding(Lg=40nm) M.Vinet et al. , SSDM 2004, Sept2004, Tokyo IST NESTOR project E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Planar Double gate by wafer bonding Best Ion/Ioff trade off @ Lg=10nm published to date!! IonN(20nm) = 1250 µA/µm IoffN(20nm)= 1.3 µA/µm Lg=20nm IonN(10nm) =1130µA/µm IoffN(10nm)=7µA/µm Lg=10nm LETI: M.Vinet et al. IEEE EDL, May 2005 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT WFET Non Planar Multigate LETI : Jahan et al, VLSI Tech Symposium, June 2005 Kyoto(Japan) Functional N-Fets tested down to Lg=10 nm Si HfO2 TiN Lg = 10 nm TEM cross-section of a 60 nm silicon finger Wfet device NMOS: ION=326µA/µm, IOFF=600pA/µm @ VD=1.2V, SS=90mV/dec, DIBL=130mV Excellent ION/IOFF ratio of 5.105 for a 10 nm non planar device and very good channel control E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Silicon On Insulator based architectures Subthreshold regime – optimizing electrostatics Subthreshold regime is limited to 60mV/decade at 300K SiO2 Si tSi L Planar Fully Depleted SOI Planar Double-gate, FinFET Ratio : tsi/L x 1/4 gate Tri-gate,W-FET SiO2 X 1/2 SiO2 Si Surrounding-gate (nanowire) Film thickness tSi required for a given L value SiO2 Si x1 B.Doyle – VLSI’03 10A-2, 2003 M. Ieong et al. Science vol. 306 Dec. 2004 X 1-2 * No direct S-D tunnel introduced … E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

From Multichannels to Nanowires (planar and 3D) Planar multichannels: Gate SiPoly /TiN/HfO2 SiChannels HM S/D SEG SOI Source Drain BOX CVD growth of single nanowire multigate devices HfO2/TiN gate stack 200 nm RTB: 3D Nanowire matrix (b) CVD growth within Al2O3 pattern nanowire matrix with HfO2/TiN gate (c) MBE growth of wire heterostucture Courtesy of : T.Ernst et al., E.Hadji et al.

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Sommaire Introduction et contexte Dispositifs CMOS : physique, effets ultimes (géometries ultimes) Feuille de route de la nanoélectronique et mise à l’échelle linéaire (ITRS and linear down scaling) Nécessaires « Boosters » pour maintenir le progrès Nouveaux matériaux pour amélioration CMOS: transport, parasites et courant de fuite Nouvelles architectures CMOS Nanoélectronique Architectures post CMOS. Opportunités mémoires Conclusions : futurs systèmes/puce(SOC), feuille de route E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

General trend towards few electron electronics E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Candidates for Post CMOS Nanoelectronics E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Coulomb blockade effect and Single Electron Transistor E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Limits: from CMOS to SET-MOS 10 -11 -10 -9 -8 -7 -6 -5 -0,4 -0,2 0,2 0,4 0,6 Vd=100µV Vd=300µV Vd=500µV Drain Current (A) Vg T=75K T=20K Lg=20nm W=10µm CEA /CEA-LETI: M. Specht et al. IEDM1999 G. Bertrand et al., Proceedings ULIS 2003 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT 10 100 2 3 Number of electrons per bit, N Flash Technology Node [nm] D V Th - max =3V NOR Flash NAND Flash Si Nanocrystals Memories (NAND ) 35nm 200 Few electron phenomena will appear in future NV memory generations Defect in conventional Flash memories (Stress Induced Leakage Current): => retention insulator Tunn.Ox Control gate Floating gate Molas et al., IEDM2004, San Francisco(CA), Dec. 2004 Non Volatile (Flash) Memories Si substrate Control gate ADAMANT Control gate Nanocrystals N= 1012cm-2, = 5nm LPCVD Si multilevel storage!! E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Molecular Memories Memory applications of molecular electronics Strong market demand High density and low cost Redundancy Few examples Porphyrins … Thermal budget > 400°C Multi-Bit/cell Bocian UC Riveside 2003 WORM Forrest Princeton 2003 Meyyappan NASA 2004 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Sommaire Introduction et contexte Dispositifs CMOS : physique, effets ultimes (géometries ultimes) Feuille de route de la nanoélectronique et mise à l’échelle linéaire (ITRS and linear down scaling) Nécessaires « Boosters » pour maintenir le progrès Nouveaux matériaux pour amélioration CMOS: transport, parasites et courant de fuite Nouvelles architectures CMOS Nanoélectronique Architectures post CMOS. Opportunités mémoires Conclusions : futurs systèmes/puce(SOC), feuille de route architectures E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Integration of new functions on chip. Future System On Chip Training, education issues to mix devices in design!! few e-memories Integration of new materials for new functions with new devices exploiting new physical phenomena Pluri and inter disciplinarity!! MEL-ARI Nanoelectronics Roadmap E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Perspectives: Dispositifs CMOS Nanoelectroniques Réduction de leurs dimensions : visibilité jusqu’à Lg=5nm(2020) /encore de nombreux défis!! Constitueront la plateforme de base de la Nanoelectronique Nouvelles fonctionnalités sur la puce=> Pluridisciplinarité Consommation énergétique constitue le défi majeur tout en gagnant en performances (Valim: sub 1V). => Optimisation : architectures des dispositifs(*) et systèmes (*) effets quantiques rôle majeur E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Merci de votre attention Construire un pôle compétitif internationalement Recherche Operationnel en 2006 4000 personnes en 2007 Merci de votre attention Industrie Education Bringing into operation a Centre of Excellence at the worldwide scale in Grenoble.   In the US and in Asia, in the field of MNT, we observe the emergence of new R&D poles, also called scientific districts. These initiatives gather huge investments at the local and federal levels. They build-up top level technological platforms, and try to attract brains coming from everywhere in the world, including Europe. Their goal is to gather in the same premises scientific excellence, critical mass, and multi-disciplinary expertise, and finally to get a sustainable worldwide leadership in nanoelectronics. It is a must for Europe to have its own such scientific districts in MNT, and indeed Europe already has: MINATEC in Grenoble will be fully operational in 2005. It will offer critical size (over 4,000 people), the proper link between education, research and industry and a competitive infrastructure based on 200 mm and 300 mm silicon platforms, in a very multi-disciplinary background. Multidisciplinarité Excellence Masse critique Plate-forme technologique 170 M€ investis par les partenaires E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Formulaire(1) Courant dans le transistor en régime linéaire: (Vd<Vdsat): Courant dans le transistor en régime de saturation : (Vd=Vdsat): A Vd=Vdsat le canal est pincé Transconductance: régime linéaire Transconductance: régime de saturation Temps de propagation par porte CMOS: td = CV/Isat si les TMOS N et P sont symétriques(Isat N=IsatP) ts=1/2 CV/(IsatN-1 + IsatP-1) si les TMOS ne sont pas symétriques Courant sous le seuil(VG<VT) E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Formulaire(2) Probabilité d’effet tunnel Tension de seuil Pente en faible inversion Effets de canaux courts(partage de charges entre la source le drain et la grille) Effet Fowler Nordheim(effet tunnel assisté par le champ électrique) Capacité de couplage grille/ canal(déplétion+effets quantiques dans le canal) VT avec contribution (déplétion+ effets quantiques) VT TMOS SOI Fortement déserté Puissance totale, Puissance dynamique P = Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd2 f E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT Flow for Future Simulations: from Poisson / Drift Diffusion to Schroedinger/Monte Carlo Corrected Boltzmann’s equation E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Downscaling … and modeling 100 nm 10 nm Simulation model Classical transport Drift-diffusion model Semi-classical transport Hydrodynamic model Monte-Carlo method dimensions Wigner function model Green function model Quantum hydrodynamic model Quantum transport 60 70 80 90 00 year E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Passive layer combine w BOx Opportunities for other materials on Silicon Material µn (cm2V-1s-1) µp (cm2V-1s-1) sth (W/m/K) Rel. K Eg(eV) Vsat(107cm/s) Si 1400 500 141 11.9 1.12 0,86 Ge 3900 1900 59.9 16 0.66 0,60 GaAs 8900 400 46 12.5 1.42 0,72 C-Diamond 1800 >1500 5.7 5.47 2,7 InSb 78000 750 _ 16.8 0.16 5,0 Well established high quality material (>40yrs experience) Oxidizable ! Silicon compatible Available in all fabs Opto Power RF applications Ge compatible Highest sth Most compact logic High short channel effect immunity Highest µn but Worst µn/µp!! Passive layer combine w BOx (thermal shunt) /graphite LETI: S.Deleonibus, ICSICT 2004, Beijing, Oct. 2004 , S.Deleonibus et al., Int.Journ. High Speed Electronics, March 2006 E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT

Perspectives: Nanoelectronics CMOS devices thermal µ+ Scaling can be foreseen down to Lg=5nm. Nanoelectronics Base platform Power consumption: major issue (sub 1V supply voltage). => Device/ system architecture optimization FDSOI: Advanced substrate (BOX, stressors, thermal shunts,…) Dual strained channels(GeOI option); Dual metal gates (Hi Perf); Metallic S&D (Schottky vs ohmic cts) New routes (LETI playground) New device architectures: Max Ion/Ioff and Low Power Multigate, Multichannels, Nanowires, Nanotubes, IMOS,… 3D integration: elementary function New SOC concepts(analog, RF, Hi Perf,Memories): compound SC/OI/Si based substrate, molecular electronics, … E2Phi Nantes Aug 22-25 2006 S.Deleonibus LETI/D2NT