Low power integrated circuits and supply management

Low power integrated circuits and supply management
Dimitri Galayko

Plan du séminaire Energy and information processing Digital circuits:
Dynamic dissipation Static dissipation Low supply voltage integrated circuits Power management: energy transfert Lossless DC-DC conversion Case study: the Dynamic Voltage and Frequency Scaling technique for the on-chip power management

Motivation: autonomie des objets communicants
Lifetime of the battery: A button 10 mA-h : if one year lifetime required, the average power is 1 μW. Operation of an autonomous sensor [Alioto et al., 2012]

Radical reduction of the consumed power is required
Digital circuits Analog/mixed circuits RF communication circuits Battery/energy management

Embedded system from the point of view of the energy
Information processing devices produce heat A question: is it inevitable? Is there a low limit of the heat production?

Physics of a memory A memory elelement is a bistable system: it has two stable states separated by a potential barrier

Physics of a memory The second low of thermodynamics: the information tends to be lost Natural transition: perturbations… Natural memory erasure A defined state: 1 bit of information Undefined state: 0 bit of information

Entropy: the measure of the desorder in the system
Natural transition: perturbations… Natural memory erasure Minimum entropy: The state of the system is known Maximum entropy: 2 possibilities to define the system state

How much energy do we need to define 1 bit of information?
According to Landauer, ! (IBM, 1961) Maximum entropy: 2 possibilities to define the system state Minimum entropy: The state of the system is known k=1, × m2 kg s-2 K-1: Boltzmann constant T: absolute temperature

Irreversibility in the digital signal processing
A NAND gate: Two inputs logical gate: four possible input states, two possible states at the output: a loss of information

Landauer principle: conclusion
There is a fundamental limit of the energy which must be spent during an irreversible information processing Presently, we are by factor above this limit – most of energy dissipation is due to interconnexion Quantum information processing: is able to approach the Landauer limit, but presently, is not suitable for implenentation of complex systems

Another way to calculate the energy limit for the information processing
The principle: the signal must be extractable from the noise The power of the signal must be  times greater than the power of the noise. Considering a thermal noise in a resistance, we have: Here k is the Boltzmann constant, B is the signal bandwidth, T is the absolute temperature

Plan du séminaire Energy and information processing Digital circuits:
Dynamic dissipation Static dissipation Low supply voltage integrated circuits Power management: energy transfert Lossless DC-DC conversion Case study: the Dynamic Voltage and Frequency Scaling technique for the on-chip power management

CMOS Inverter: a reminder
A CMOS circuit

Dynamic dissipation Dynamic phenomena in a CMOS circuit
"ICT - Energy - Concepts Towards Zero - Power Information and Communication Technology", edited by Giorgos Fagas et al.

Dynamic dissipation Dynamic phenomena in a CMOS inverter

Dynamic dissipation Dynamic phenomena in CMOS inverter:
energy losses in capacitors

Dynamic dissipation Reduction of the dynamic consumption of CMOS circuits: A compromise between the consumed energy and the speed The propagation time of a NOT gate: Lost energy during the switching:

Dynamic dissipation Dynamic energy dissipation:
Cyclic charging of the capacitors of MOS transistors The energy lost in one cycle is proportional to Vdd2 and to the load (parasitic) capacitance The power is proportional to the frequency

Dynamic dissipation Logical gate: the short-circuit current
Depends on the gain of the cell at VDD/2 and of the transition time

Evolution of the dynamic dissipation with the progress in the technologies
"ICT - Energy - Concepts Towards Zero - Power Information and Communication Technology", edited by Giorgos Fagas et al. Top Down: consommation globale des processeur Bottom-Up: consommation calculée à partir du nombre de Transistor La différence: les pertes dans les connexions

Reduction of dynamic dissipation
How to reduce it? To lower Vdd : but we increase the delay, so we slow down the circuits We can lower Vdd while lower Vth in order to compensate the delay degradation: but in this case, we increase the static losses (cf. below) Reduction of CLoad: miniaturization Reduce the activity of the circuit (number of switching per second)

Reduction of dynamic dissipation
Techniques of reducing of the energy consumption: « fine » regulation of the circuit operation Reduction/modulation of the clock frequency, alternative techniques of clock generation Disconnecting inactive circuits: multi-Vth CMOS technologies A fine adjustment of the supply voltage on chip, multiple supply zones Use of small size cells Alternative architectures of logical gates (adiabatic logics, etc…) …

Reduction of activity Reduction of activity in the circuits: the most efficient method for reduction of the dynamic consumption The reason is: f is the frequency of switching Methods of the energy reduction: Clock gating

Activity reduction: a clock gating
The idea: to disconnect (to gate) the clock for the blocks which are not active

Activity reduction: a clock gating
A better architecture of the clock gating: a synchronous clock gating

Activity reduction: a parallelization
By parallelizing the information processing, we reduce the speed of each processing channel, and so we release requirement on the individual gates delays : we can diminish VDD and the component sizes

Activity reduction: a parallelization
Example : series-to-parallel register

The activity reduction allows a reduction in Vdd
The problem: the logical levels compatibility.

The activity reduction allows a reduction in Vdd
The solution to the level compatibility: use of level shifter based on circuits with negative resistance (flip-flops) High voltage Low voltage

Reduction of « glitches » : reduces the overall circuit activity
The « glitches » are transient states of a logical circuit due to combinatory logical operations. Indeed, before a right value is established at the output, the output displays a sequence of transient wrong values. If the output is loaded by a large capacitive load, the energy Solutions 1 : a buffer register, which « masks » the capacitive load

Réduction d’activité : les « glitches »
Solutions 2 : optimisation of the architecture of circuit so to reduce the glitches at the output. A pre-processing of the inputs is one of the techniques For example, we can gate the intput to which the output value is not sensitive

Outline Energy and information processing Digital circuits:
Dynamic dissipation Static dissipation Low supply voltage integrated circuits Power management: energy transfer Lossless DC-DC conversion Case study: the Dynamic Voltage and Frequency Scaling technique for the on-chip power management

Static losses When the logic intputs of CMOS gates are constant, there is static (leakage) currents which yields static power dissipation In deep submicron technologies, these losses tend to dominate over dynamic dissipation [Dhar 2011]

Static losses Static losses : are due to leakage current in the transistors 1) Grid current by tunnel effect (dominant for L<100 nm) 2) Subthreshold conduction 3) Grid Induced Drain Current(L< 50 nm) 4) PN junction current (dominant for L> m)

Mechanism of static leakage current [1]
Plot of the gate current by tunnel effect as a function of the technology node and the applied voltage Composants du courant de grille

Mechanism of static leakage current
Plot of the gate current by tunnel effect as a function of the gate oxide thickness and the applied voltage, [Dhar 2011]

Subthreshold current : Even when Vgs=0, there is a current if Vds≠Vth This is a parasitic effect. However, the subthreshold conduction can be used in the circuit operation with very low energy consumption.

Courant de fuite « drain-source » du à la faible inversion en fonction de la tension d’alimentation et de la température

Consommation dans les circuits numériques
Courant de fuite de drain dû aux différents facteurs, [Dhar 2011]

Consommation dans circuits numériques
Impact conjoint des pertes statiques et dynamiques: il existe un point d’énergie minimale

Plan du séminaire Energie et traitement de l’information
Circuits numériques: Dissipation dynamique Dissipation statique Circuits numériques à tension d’alimentation réduite Gestion de consommations : transferts d’énergie Conversion de tension DC sans pertes Exemples de cas : systèmes de gestion d’énergie sur puce par la technique DVFS

Consommation dans les circuits numériques
Jusqu’où peut-on baisser la tension d’alimentation ? La limite basse de VDD est posée par : -- La tension thermique Vt (2Vt est le minimum théorique) -- déséquilibre intrinsèque entre les transistors N et P (le minimum est relevé à 3 Vt) -- Les variation des paramètres des composants (8-9 Vt, c.a.d., mV en techno 65 nm)

Consommation dans circuits numériques
Conséquence de réduction de la tension d’alimentation: augmentation des délais. Il est plus intéressant de considérer l’énergie d’une opération Le TP: étudier la consommation d’une cellule d’additionneur pour de très faibles valeurs de tension

Transferts d’énergies électriques
Le problème de transfert d’énergie électrique se pose Lorsqu’il faut générer plusieurs tensions d’alimentation à partir d’une source de tension DC Lorsqu’il faut transferrer l’énergie depuis ou vers un Condensateur Dans les systèmes ultra basse consommation, il s’agit de le faire avec pertes minimales Il existent des limitations/difficultés de nature fondamentales, qu’il convient d’étudier

Transfert d’énergie d’une source de tension vers une capacité Réutilisation d’énergie d’une capacité Conversion DC-DC

Basics about energy transfer between capacitors
Configuration 1 : two capacitors, equal C Their energy : Configuration 2 : They are connected Their energy : C C C C U0 Q0 U0/2 Q0/2 U0/2 Q0/2 Half energy is lost during the transfer ! Solution ? Use of a self-inductor Tutorial ICECS D. Galayko, E. Blokhina

Principle of DC-DC conversion
3 stages : C C W=0 W=CU02/2 C W=CU02/2 U Q0 W=CU02/2 -U0 I=0 I=Imax I=0 t=0 : a non-charged inductor is connected. 0<t<t1=0.25∙2π(LC)1/2: an energy transfer toward inductor t=t1 : All initial energy is in the inductor t1 <t<t2=0.5∙2π(LC)1/2: An energy transfer toward the second capacitor At t2: all energy is in the second capacitor Tutorial ICECS D. Galayko, E. Blokhina

Abaisseurs de tension inductifs

Abaisseurs de tension à capacités commutées

Convertisseurs DC-DC Convertisseurs DC-DC à plusieurs sorties pour générer des tesions sur les puces multi-IP M. Belloni, E. Bonizzoni, E. Kiseliovas, P. Malcovati, F. Maloberti, T. Peltola, T. Teppo, A 4-Output Single-Inductor DC-DC Buck Converter with Self-Boosted Switch Drivers and 1.2A Total Output Current, ISSCC 2008

Convertisseurs DC-DC M. Belloni, E. Bonizzoni, E. Kiseliovas, P. Malcovati, F. Maloberti, T. Peltola, T. Teppo, A 4-Output Single-Inductor DC-DC Buck Converter with Self-Boosted Switch Drivers and 1.2A Total Output Current, ISSCC 2008 Schéma du convertisseur DC-DC multi-entrée multi-sortie Application: système à plusieurs sources d’énergie

Convertisseurs DC-DC Schéma de contrôle de switches
M. Belloni, E. Bonizzoni, E. Kiseliovas, P. Malcovati, F. Maloberti, T. Peltola, T. Teppo, A 4-Output Single-Inductor DC-DC Buck Converter with Self-Boosted Switch Drivers and 1.2A Total Output Current, ISSCC 2008 Schéma de contrôle de switches

Plan du séminaire Dissipation dynamique Dissipation statique
Gestion de consommations : tranferts d’énergie Conversion de tension DC sans pertes Exemples de cas : systèmes de gestion d’énergie sur puce

Présentation des cas E. Beigné et al., A localized Power control Mixing Hopping and Super cut-off techniques within a GALS NoC : système GALS avec tension d’alimentation / fréquence variable par zones isochrones B. Mishra et Subthreshold FIR Filter Architecture for Ultra Low Power Applications, PATMOS 2008 conference, sur une architecture de circuit arithmétique ultra basse consommation M. Belloni et al., 24.6 A 4-Output Single-Inductor DC-DC Buck Converter with Self-Boosted Switch Drivers and 1.2A Total Output Current, ISSCC 2008 conference - sur un générateur multitensions sur puce J. Song et al., An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling, CICC 2006, sur un générateur de tension d’alimentation réglée sur la valeur souhaitée du délais Lhermet et al., On chip post-processed microb attery powered with RF and thermal energy through a power management circuit, sur un générateur de tension multisource avec gestion d’énergie

VDD ou la fréquence ? VDD est lié au délais, donc à la fréquence
D’ailleurs, la fréquence est aussi liée à la consommation Donc, l’idée est de contrôler les deux… Travaux d’E. Beigné et al. E. Beigné et al. Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC , ACM/IEEE International Symposium on Networks-on-Chip,   

Variabilité de fréquence et de VDD sur toute la puce
Solution connue sous le nom DVFH (Dynamic Voltage Frequency Hopping). Travaux d’E. Beigné, I. Miro et al Contexte: système multi IP (NOC, …) rassemblant plusieurs IPs sur la même puce

Réponse à une large variabilité des paramètres du procédé

Idée : Pour une vitesse de traitement donnée, il existe une fréquence d’horloge optimale, avec une tension d’alimentation optimale

Avec seulement 3 niveaux de tensions d’alimentation, en utilisant la technique de voltage dithering, on arrive à moduler la tension d’alimentation effective d’un bloc [I. Miro et al., Journée Synchronisation GDR SOC SIP, 2014]

Génération de l’alimentation variable

Solution connue sous le nom DVFH (Dynamic Voltage Frequency Hopping). Travaux d’E. Beigné et al Un nœud de réseau

Bibliographie K. Roy, S. C. Prasad, Low Power CMOS VLSI circuit design, Wiley & Sons, 2000 J. M. Rabaey, Digital Integrated circuits: a design perspective, Prenstice Hall, 1995 Thèse de doctorat de Sylvain Miermont, 2008, INPG, Grenoble Dhar et al., Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications, VLSI Design, 2011

Low power integrated circuits and supply management

Présentations similaires

Présentation au sujet: "Low power integrated circuits and supply management"— Transcription de la présentation:

Présentations similaires

Notre projet

Feed-back

Entrer

S'autoriser via un réseau social:

Low power integrated circuits and supply management

Présentations similaires

Présentation au sujet: "Low power integrated circuits and supply management"— Transcription de la présentation:

Présentations similaires

Notre projet

Feed-back