1 ActivitésMicroélectroniques sur LSST Hervé Lebbolo pour le groupe LSST électronique LAL / LPNHE Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

2 Telescope and site : Cerro Pachon, Chile LSST : Large Synoptic survey Telescope Temps de pose : 15sLecture : 2s Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

3 CRYOSTAT Plan focal & Rafts TOWER CCDs + front end electronics 180K operation An autonomous, fully- testable and serviceable 144 Mpixel camera RSA RCC FEC RAFT 9 CCDs coplanarity 13.5mm 92% fill factor 4K x 4K CCD 10mm pixels = 0.2” extended red response 16 outputs 5mm flatness 4 cm 21 rafts, with 9 CCDs each CCD : 16 * 1Mpixel Camera : ~3Gpixel Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

4 Chaîne de lecture de la caméra 18 bit ADC CABAC ASPIC: Analogue Signal Processing Integated Circuit CABAC: Clocks And Biases Asic for CCD Readout : 500kHz RCM Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

5  8 channels dual slope integrator  173K  CCD 550kHz – up to 1MHz  Power dissipation : 25mW / channel  Power Supply 0/5V with respect to reference = 2.5 V  Noise :  ~5nV / √Hz maximum noise density [ 5 to 6 e- read noise (10nV/ √ Hz) for the whole CCD chain]  7µV rms for 500ns integration [< 2 e-]  Crosstalk : level [ 0.01% (goal) % (max) ]  Full Well capacity :  90keˉ [150keˉ max] ie ~400mV max input  Linearity : 0.5% [defined over to full well scale]  Differential outputs  Output Load : 50pF // 1 k Ω  Nap mode ASPIC Requirements Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

6 CCD Reset ASPIC Reset CCD Output Integration Time Tint Isolation Time ADC S/H Dual Slope Integration sequence One of the 2 differential channel output Ramp Down (integrate noise) Ramp Up (integrate signal + noise) Read Out Method : Dual Slope Integration Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

7 ASPIC (2)  3 programmable input amplifier gains : 2.5 – 5 – 7.5  to deal with CCD gain spread.  3 integration time constants : 500ns – 1µs – 1.5µs  to deal with CCD readout frequency. baseline : {gain 5 & 500ns integration time} Input amp Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

8 Schéma de Base Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

9 ASPIC 2 layout Techno : CMOS 0.35µ 5V Vendor : AMS Package 1 : CQFP100 Package 2 : QFN100 avec bottom pad pour un meilleur contact thermique Surface : 2,7*3,8 mm² Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

10 ASPIC2 tests bench Front End Board (cryo or room temperature) Custom Back End Board (8*18 bit ADC Altera FPGA) PC + LabView PC + LabView generators Programmable Power Supplies Programmable Power Supplies ASPIC (2) Switches Board Programmmable attenuator Programmmable attenuator signal ck 127dB / 1dB step Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

11 USB FIFO External trigger ADC channel FPGA Input (from ASPIC) Output to ASPIC : clocks, commands Gain switches Output to CCD Back End Board Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

12 Cold Front end (LPNHE) Flex cable and 37-pin connector (17 grounded) Shielding with thermal break (mesh) Temperature sensors & heating Outputs and power supply Clocks and settings Inputs 4 CCD inputs Cooling: front-end card connected to nitrogen circuit Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

13 LAL Cold Test Stand QFN Packaging With bottom pad QFN Packaging With bottom pad Sub Micro D connectors 8 input Clamp for X talk measurements 8 input Clamp for X talk measurements Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

14  Chip-to-chip rms dispersion = 2%  In-chip dispersion rms dispersion = 0.3% on average – 0.5% at most ASPIC II Measurements : Gain Gain measured over 37 chips *: R&C extraction Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

15 ASPIC II Measurements : Gain Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

16 Effect of input amplifier bias ASPIC II Measurements : Noise le bruit peut être encore diminué si le budget puissance augmente Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

17 gain=5 (6), RC=500ns  residu: 0.3% ASPIC 2 Linéarité gain=2.5 (3.9), RC=500ns  residu: 0.4% Requirement : < 0.5 % over full well range Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

18 Measurements : Crosstalk Y axis = source X axis = victim  Xtalk asymetric : injecting a signal in the ch 7 generate more crosstalk than injecting a signal in the ch 0.  When the ASPIC II input stage saturated, the Xtalk also saturates :  Xtalk is probably dependant of the amplitude at the output of the first amplifier. Notice:  postlayout simulations don’t show any crosstalk effects.  ASPIC I had a smaller Xtalk ( < % ) than the ASPIC II and no programmable gain. Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

19 Effect of the integrator reset width on the channel memory 150ns 200ns 250ns Measurements : Memory Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

20 Mesure de la réponse à un niveau DC : efficacité de l’annulation du bruit de reset (kT/C) du CCD et de la dérive du signal d’entrée (couplage AC) Asymétrie : 0,07% ( bruit de reset CCD : 60 e ⁻  erreur 0,04 e ⁻ ) Asymétrie totale ~ asymétrie gains * asymétrie intégration ASPIC2 TESTS DC Asymétrie ASPIC input G+ G- S+ S- Different gain / Same Time Constant Ramp down Ramp up Difference = 0 Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

21 Tests à froid sur long terme : vieillissement ? dégradation des performances ? Mesures plus fines des effets mémoire, Xtalk, impact des temps d’isolement sur le bruit Mesures avec le CCD Augmentation du « gain » et du full well (150ke) du CCD d’e2v  diminution du gain (augmentation du bruit) Programmation plus fine du temps d’intégration et du gain (2*4bit) Mode transparent (monitoring des signaux CCD) Sonde de température ? Programmation par lien série Amélioration de la vitesse de « réveil » ASPIC 2 suite et fin  ASPIC 3 Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

22 ASPIC 3 suite Mode transparent Soumission prévue début 2013 Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

23 CABAC : clock and biases asic for CCD IΦ0IΦ1IΦ2IΦ3IΦ0IΦ1IΦ2IΦ3 IΦ3IΦ3 Fournir les horloges (série et parallèle), les polarisations et les alimentations des amplis de sortie des CCD Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

CCD requirements OD &Biasese2v CCD250ITL/STA1920AHPK S exposereadouterase Back substrateBS-70BB-10VBB50300,2 Front substrateFS0SUB0VGR000 GuardGD30SC Output DrainVOD30OD27VOD Output GateVOG2OG-2VOG-5 Reset DrainVRD18RD15VRD Test inject source----VISV Test injectgate----VIGV000 ClocksHILOHILOHILO erase Parallel Serial100, Reset Gate Summing Well Transfer Gate Capacitances (estimated) Parallel per phase64nFunavailable25nF(2K x 1K device) Serial per phase320pFunavailable50pF RGunavailable 10pF SW----10pF TG pF baseline

25 CABAC requirements OD and Biases: –2 OD : 8 bit programmable level from 13 to 36V, 16 mA capability each, exposure & readout levels, load : 100Ω +.1µF –1 RD : 8 bit programmable level from 13 to 36V, 1kΩ +.1µF load, electronic calibration pulser –1 GD : 8 bit programmable level from 13 to 36V, 1kΩ +.1µF load –1 OG : 8 bit programmable level from 0.1 to 4.8V, 1kΩ +.1µF load –1 spare0 : 8 bit programmable level from 13 to 36V, 1kΩ +.1µF load –1 spare1 : 8 bit programmable level from 0.1 to 4.8V, 1kΩ +.1µF load Clocks : –4 parallel, 8 bit programmable current capability (max 300mA), common voltage rails (ΔV = 20V max), exposure/readout modes (static current divided by 10) –4 serial, 8 bit programmable current capability (max 16mA), 2 voltage rails (3+1) (max 20V), exposure/readout modes Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

26 CABAC requirements Readout & Exposure modes input independant from serial programing Temperature sensor (current source + diode connected mos transistor) Multiplexor : Possibility to output 2 of any signal provided by CABAC or external input for monitoring, output can be disabled for paralleling Operates at 173K (?) Programmation by serial link with read back & asynchronous reset Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

27 Process Process : AMS CMOS 0.35µm 50V, H35B4D3 Care has to be taken on Vgs for lifetime (LTacc) Durée de vie = 10 ans/LTacc Cryo temp lifetime : no guarantee from AMS Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

Prog Serial link // & Serial Clocks // & Serial Clocks OD & Bias OD & Bias Calib pulser Calib pulser Multiplex eur From CCD, Aspic, FEB Timing Synoptique CABAC Vers CCD Vers BEB From BEB Temp Power Supply

29 8 bit DACVCCS Current mirror Current mirror LVDS receiver Level translator Clock Switch VDD upper VDD lower Current setting LVDS clock Clocks Exp/Ro VDD command Clock Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

30 Clocks scheme Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

31 Parallel Clock scheme Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

32 Parallel Clock layout Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

33 Readout setting register OD (& biases) Voltage Amplifier OD VDD Exp / RO 8 bit DAC Exposure setting register OD Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

34 OD, RD, OG GD, Spare, Ext, Ext Serial, RG Parallel OD, Ext Temp, Spare, Ext, Ext Serial, RG Parallel 2:1 Mux Out 0 Out 1 Dual 16 to 1 multiplexer 8 : 1 Active Mux 8 : 1 Passive Mux 8 : 1 Active Mux 8 : 1 Passive Mux Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

35 Electronic Calibration Pulser implementation : Pulser CCD trig To aspic Reset RD calib pulse Pulser enable CABAC Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

36 Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012 IΦ0IΦ1IΦ2IΦ3IΦ0IΦ1IΦ2IΦ3 IΦ3IΦ3 Reset calib pulse Electronic Calibration Pulser implementation :

37 Serial link : Place & Route ~570*570µm² Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

Full Cabac_0 layout Area : ~36mm²

TEST_0 AMS HV CMOS chip for HV & Cold tests purpose 5 mos transistors : 1 large (5000*3) 20V thick oxyde Pmos 1 large (5000*2) 20V thick oxyde isolated Nmos 1 (100*3) 20V thin oxyde Pmos 1 (100*2.5) 20V thin oxyde isolated Nmos 1 (100*3) 50V thick oxyde Nmos One high level bias with 8 bit DAC One temp sensor

TEST_0 layout Area : 5.4mm² 10 chips packaged in QFN36 15 naked dies Sent early november Delivred in february

41 TEST_0 test bench TEST_0 PCI DIO 96 PCI DIO 96 Host Programmable Power Supply Programmable Power Supply Relay Board Relay Board prog usb Scope Vds, Vgs Ammeter Keithley Ammeter Keithley Id, Ib Vbias,.. Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

42 TEST_0 tests Keithley Programable Power supplies Relay board Hot tests board Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

43 Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012 Transistors tests Keithley Alim_P_source (0-20)Alim_N_drain (0-20) Alim_N_gate (0-4) Alim_P_Gate (0-3,1)

44 Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012 CABAC test bench CABAC Test FE Capacitors Analog Digital Daughter Board FPGA Evaluation Board Ethernet/usb Host hot Hot/ cold hot Scopes

45 ADC série 18b 1MS AD7982 (x13) CABAC Tests Bench Altera EP3C120 Altera EP3C120 Ethernet GEDEK OD Mux Out OD Spare GD OG RD 13SDO RO/Exp & Serial Link HSMC-B Analog daughter board FPGA cyclone III dev board 2 SCOPES 4 channels + external trigger (WaveAce224) Trigger SMA out 18 CNV SCK Trigger_ext Trigger_out ADC série 16b 6MS AD7625 (x2) ADC série 16b 6MS AD7625 (x2) 2SDO 2CNV 2SCK DAC 0 SCLK SYNC SDIN DAC n DAC 6 SDO BIAS 4 MUX CABAC 8ck / 1pul 9p CK CABAC LVDS CMOS 7 30 pins LVDS (15 pairs) 28 pins 2.5V-LVCMOS Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

46 The End Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012