SKIROC status LAL – EUDET France – 05/04/2007. Common DAQ Slice FE FPGA PHY VFE ASIC Dat a Clock+Config+Control VFE ASIC VFE ASIC VFE ASIC Conf/ Clock.

Présentation au sujet: "SKIROC status LAL – EUDET France – 05/04/2007. Common DAQ Slice FE FPGA PHY VFE ASIC Dat a Clock+Config+Control VFE ASIC VFE ASIC VFE ASIC Conf/ Clock."— Transcription de la présentation:

1 SKIROC status LAL – EUDET France – 05/04/2007

2 Common DAQ Slice FE FPGA PHY VFE ASIC Dat a Clock+Config+Control VFE ASIC VFE ASIC VFE ASIC Conf/ Clock - Timing is the same for all detectors - Number of channels involves embedded electronic for all detectors -Outputting of data is done the same way for all detectors  Back-end of very-front-end shall be common for all detectors VFE AsicFE electronicDetector FE of VFE BE of VFE Concentrator

3 Time considerations time Time between two trains: 200ms (5 Hz) Time between two bunch crossing: 337 ns Train length 2820 bunch X (950 us) Acquisition 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) 1% duty cycle IDLE MODE 99% duty cycle 199ms (99%) analog detectors only

4 Read out : token ring Acquisition A/D conv.DAQIDLE MODE Chip 0 Chip 1 Acquisition A/D conv.DAQIDLE MODEIDLE Chip 2 Acquisition A/D conv.IDLE MODEIDLE Chip 3 Acquisition A/D conv.IDLE MODEIDLE Chip 4 Acquisition A/D conv.IDLE MODEIDLEDAQ Chip 0Chip 1Chip 2Chip 3Chip 4 5 events3 events 0 event 1 event 0 event Data bus

5 Acquisition mode in test beam  No time measurement  Synchronous hold validated by internal trigger BCID NN+1N+2 Trig OR Trigger_validb Hold Machine sync. Hold Peaking time Valid_hold (analogue memory address) kkk+1

6 SKIROC presentation - ECAL read out - Silicon PIN detector - 36 channels -Compatible new DAQ

7 Main features  Designed for 5*5 mm² pads  36 channels (instead of 72 to reduce cost of prototype)  Detector AC/DC coupled  Auto-trigger MIP/noise ratio on trigger channel : 16  2 gains / 12 bit ADC  2000 MIP MIP/noise ratio : 11  Power pulsing Programmable stage by stage  Calibration injection capacitance  Embedded bandgap for references  Embedded DAC for trig threshold  Compatible with physic proto DAQ Serial analogue output External “force trigger”  Probe bus for debug  24 bits Bunch Crossing ID  SRAM with data formatting  Output & control with daisy-chain Digital on FPGA for debug

8 One channel

9 Digital

10 Block scheme of SKIROC Ch. 0 Ch. 1 Analog channel Analog mem. 36-channel Wilkinson ADC Analog channel Analog mem. Ch. 35 Analog channel Analog mem. Bunch crossing 24 bit counter Time digital mem. Event builder Memory pointer Trigger control Main Memory SRAM Com module ECAL SLAB

11 PCBs

12 FEV4 : New PCB description  Compatible physics prototype  Same size as FEV3  1 active wafer (instead of 2 for FEV3)  Chip buried in the PCB

13 FEV4 – stack up description TOP L2 L3 L4 L5 L6 L7 BOT Single sided Double sided Single sided 950µm ILC_PHY4 SIG/GND GND VCC SIG/GND GND PADS

14 FEV4 – signal density Difficulty are already foreseen to carry signals from one stitchable PCB to another

15 FEV4 duty  Chip on board test First prototype of chip in board  Thin PCB coupling measurement  Chip in beam test Technology is 0.35µ Analog part is very close to final version Digital missing  Power pulsing test

16 FEV4 – missing features  5*5 mm² pads  Stitching  Daisy chain  Flat buried chip ILC_PHY4

17 Planning EUDET, ANR, etc.

18 Planning ANR

19 Planning Eudet Le module EUDET doit être terminé pour mi 2009 Nous nous accordons 6 mois de contingency L’électronique doit partir en prod en mars 2008 (+6 mois max) SKIROC sera testé à l’ordre 1 en septembre 2007  SKIROC 2 proto soumis fin 2007  Production mi 2008 ( 3 mois de retard) Gestion des risques à étudier, ce planning semble le meilleur compromis risque-retard mais il est très optimiste.

20 Différence EUDET-Module 0 Calibration hors chip Quelques composants à prévoir dehors (bord de slab) Signaux analogiques sur le slab (calibration pulse) Plus de signaux sdur le PCB (pas de sous adressage, plusieurs Clk) Gamme dynamique réduite à 2000 MIP Auto trigger par chip dans eudet, par voie dans module 0 ?

21 STATUS  Chips are due very soon MPW delayed by a couple of weeks  Test board is in fab 3 PCBs are due for next week 1 PCB in hand Assembling in house of the first PCB :now Firmware is in developpment Labview software is in development  First results for the next CALICE meeting Analogue measurements  Some more at LCWS