TREND GRANDproto DAQ system

Présentation au sujet: "TREND GRANDproto DAQ system"— Transcription de la présentation:

1 TREND GRANDproto DAQ system
Olivier Martineau-Huynh 27/03/2014

2 TREND 2013-2016 Objectif scientifique
Objectif: faire fonctionner un réseau radio de détection de gerbes cosmiques de manière totalement autonome. Contrainte: faire une (très) bonne réjection des événements de bruit de fond. Outil: Empreinte au sol

3 Shower axis EAS signal Background

4 TREND 2013-2016 Objectif scientifique
Objectif: faire fonctionner un réseau radio de détection de gerbes cosmiques de manière totalement autonome. Contrainte: faire une (très) bonne réjection des événements de bruit de fond. Outil: Empreinte au sol:  pour les gerbes inclinées

5 TREND 2013-2016 Objectif scientifique
Objectif: faire fonctionner un réseau radio de détection de gerbes cosmiques de manière totalement autonome. Contrainte: faire une (très) bonne réjection des événements de bruit de fond. Outil: Empreinte au sol:  pour les gerbes inclinées Polarisation ( ?): signal EAS linéaire & perpendiculaire à direction d’origine et au champ géomagnétique (au 1er ordre).

6 Principe mesure polarisation
Sur toutes antennes triguées, mesure de 3 amplitudes Vx (EW), Vy (NS) et Vz (vert) Calcul de h = atan[Vy/Vx] b = atan[(Vx²+Vy²)0.5/Vz] z b P x h y

7 Polarisation attendue pour des gerbes
Simulations donnent des signatures très spécifiques pour les valeurs de h et b associées aux gerbes atmosphériques. Point d’impact de la gerbe (q=66°, j = 354°) Antennes triguées Pour cet exemple h~5° et b = 88° sur toutes les antennes ( polarisation EW)

8 GRAND prototype Prototype array of 35 antennas ( )
+ 21 scintillators ( ) Principle of EAS selection: For all events detected: Measure polarization on all triggering antennas Select events with polarization pattern compatible with EAS. Offline cross-check with scintillator data. Allows a quantitative evaluation of the EAS selection procedure. Array along 21CMA North-South baseline (fibers for signal transmission) Scintillator array developped under IHEP lead (NSFC proposal)

9 3-polar antennas Active antennas.
Asic LNA produced by SUBATECH-CODALEMA. 6 prototypes succesfully deployed in January & March 2014 in Ulastai. On-going tests of the antennas.

10 Signaux attendus Mesures sur site oscilloscope, avec 44dB amplification) 50mV 100ns

11 Signaux attendus Simulations Signal Signal + bruit typique

12 Signaux attendus Onde elm incidente (enveloppe) convoluée à la réponse de l’antenne 80MHz) Short waves FM Band

13 Signaux attendus Gamme dynamique: Simu @ 1017.5eV: V in [100µV-10mV]
+ amplitude a Energie => Besoin d’une gamme dynamique de 1000

14 DAQ Contraintes: Données supplémentaires:
Timing du ± 30ns ou mieux pour permettre la reconstruction du signal. Mesure précise des amplitudes Vx, Vy et Vz du signal requise -> numérisation précoce du signal (au pied de l’antenne). Données supplémentaires: Signal ~80MHz, mais info physique (amplitude et durée) dans l’enveloppe seulement… Fibres optiques -> DAQ + alim 220V en place (cet été).

15 Analog shaping No need to record full signal trace. Enveloppe recording could be enough as long as output amplitude is proportional to input. Would allow slower sampling: easier (and cheaper) DAQ.

16 Signal analog shapping
A: GENERAL DAQ SCHEME FOR ONE DETECTION UNIT Antenna signals or 75Ω load (switch driven by FPGA command) Upstream: Commands & parameters Analog trigger module Threshold value Trigger inhibit FPGA Trigger bypass Downstream: data Time stamping Trigger order GPS 1Hz clock (st=30ns) Digitized data Signal sampling Antenna signal Ch1 Signal analog shapping Antenna signal Ch2 Antenna signal Ch3

17 Possible mechanical design
Box has to be dust & raintight + no elm radiation BUT allowing heat dissipation. 9 analog independant encapsulated elements to be screwed on a metalic plate in electrical contact with the external box (same as present in TREND-50). Filter MHz Integrator/ power detector ADC LNA ASIC Filter MHz G=15dB Integrator/ power detector ADC LNA ASIC Filter MHz G=15dB Integrator/ power detector ADC LNA ASIC G=-10dB BiasTee used to power ASIC LNA on antennas. To be plugged to coax cable going to antenna. Trigger module FPGA 3 antenna channels Bias Tee Bias Tee Optical interface Bias Tee ALIM TRANSFO 220V~ to 12V- GPS 220V~ Digital card

18 B: analog shaping Test of signal integration with simulations
Integrating filter: H(w) = 1/(1+j(w/wc)2) With fc=wc/2p=39MHz Gain Phase (°) Test with data for background & simulated events for signal.

19 Integration (fc=39MHz) + sampling at 80MS/s preserves signal shape.
Input ( ) : simulated EAS signal Output: clean signal (duration~150ns) Input ( ) : bckgd event (TREND data 1GHz sampling) Output: dirty signal (duration~600ns) Legend: input signal Output signal Output signal after 100MHZ sampling Integration (fc=39MHz) + sampling at 80MS/s preserves signal shape.

20 Amplitude measurement
Not so linear! … Better go to power detectors?

21 Backup

22

23 Componant list ADC: 12bits+100MSPS FPGA: CYCLONE V 5CEFA4F23C6N
Standard performances are OK. Max price: 100€/unit FPGA: CYCLONE V 5CEFA4F23C6N (40€/unit in France) GPS: UBLOX LEA-6T (60€ / unit in France, antenna not included) Optical interface: Ethernet (50€ for one transmitter + receiver pair)

24 R&D on signal shaping to be done by TREND.
Software & user interface to send commands & retrieve data to be done by TREND. One fiber per detection unit: commands sent upstream, data + monitoring downstream. Enough computers to deal with the expected data flux (on average: 2.2MB/s/unit) should be considered. Go for standard solutions: FPGA programmation language should be VHDL. Ethernet much prefered over home-made protocols. Distributed clock as a back-up solution.

25 C: TRIGGER Threshold 1 (updated at ~Hz rate from uplink fiber) FPGA
Trigger module Trigger by-pass Comparator 1 Trigger inhibit Ch1 Th. 2 Comparator 2 OR AND Ch2 Th 3 Comparator 3 Ch3 Trigger order

26 Interface Eth fiber 1Gb/S
D: SAMPLING 12-bit ADC for each channel (& 3 channels per detection unit) 5µs event size  MSPS. FPGA ADC Circular Buffer Memory FIFO Interface Eth fiber 1Gb/S ADC Circular Buffer Memory FIFO ADC Circular Buffer Memory FIFO Continuous writing to circular memory (depth= 1Kx12-bit) At trigger signal, transfer of data of interest to FIFO for 3 channels in parallel. Duration~ 15nsx500=7.5µs. Trigger inibited meanwhile. After transfert, trigger possible again. FIFO (2Kx12-bit) to un-randomize entry flux (FIFO size ~ 4 events). Transfert of total event (3x500words serialized + header) through fiber. Expected data rate: 3x500x12bx1000Hz/8 ~ 2.2 MBy/s

27 E: Time stamping A time stamp provides absolute time info at given moment (the time of trigger). Baseline solution: an internal 32bits-100MHz counter re-synchronized each second on the 1Hz signal from a GPS clock. Expected precision: 30ns. Important notice: this time stamping is initiated by the trigger module. It is totaly independant from the signal sampling and ADC sampling frequency.

28 Timing precision Time stamping unit (GPS+100MHz counter) Trigger Generator Time stamp t*i 10000 realisations Gate generated at time ti A 30ns resolution means that t*i-ti should be within ±30ns in 66% of the cases. t*i –ti [ns]

29 Time stamping Alternative solution: keep track of ADC counts since the beggining of the run and record ADC count for each trigger (same as present TREND DAQ). As all ADC run at the same pace (100MSPS), relative time info between all antennas can be determined if their relative offset at start of run is determined. This can be done by sending a calibrating signal at a specific time seen by all antennas. To perform ADC count: count the number of full circular buffers + position of pointer in present buffer at time of trigger. This method has not been validated yet. This is R&D we want to test. Therefore we also need GPS method (see before).

30 Calibrating signal seen by all antennas
Channel x of antenna A 1 2 3 4 i-2 i-1 i i+1 : ADC count corresponding to trigger instant on this antenna. Channel y of antenna B 1 2 3 4 i-2 i-1 i i+1 Channel y of antenna B 1 2 3 4 i-2 i-1 i i+1 run t=0 t (ns) Undetermined relative offset when ADCs start [~ constant over run duration] Comparison of ADC count at trigger instant allows determination of relative ADC offsets.