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Estimation de Performances Multicritères pour les Systèmes sur Puce (SoC) Jean Luc Dekeyser.

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Présentation au sujet: "Estimation de Performances Multicritères pour les Systèmes sur Puce (SoC) Jean Luc Dekeyser."— Transcription de la présentation:

1 Estimation de Performances Multicritères pour les Systèmes sur Puce (SoC) Jean Luc Dekeyser

2 Diverse fonctionnalités, rapide, petit, pas cher… Time-to-prototype Time-to-market Flexibilité (Maintainability) Faible puissance/ Dissipation thermique (durée de vie des batteries) Coût de production Adaptation rapide avec les nouveaux standards Fiabilité, sécurité… Les SoC d’aujourd'hui doivent répondre à ces paradigmes!!! Motivations: Tendance des produits

3 ARM PrimeXsys Wireless platform: Standard SoC Kernel based on ARM926EJ-S Source: © ARM

4 Triscend A7 CSoC ARM7TDMI + FPGA Source: © Triscend

5 ASIP: reconfigurable microprocessor Tensilica Xtensa Source: © Tensilica

6 Motivations: Plateformes cibles Scheduling/Arbitration proportional share WFQ staticdynamic fixed priority EDF TDMA FCFS Communication Templates Architecture # 1 Architecture # 2 Computation Templates DSP EE Cipher SDRAM RISC FPGA LookUp DSP TDMA Priority EDF WFQ RISC DSP LookUp Cipher EE EE EE EE EE EE static Quelle architecture est adéquate pour notre application?

7 Exploration de l’espace de solutions ApplicationArchitecture Mapping Analysis Cette méthodologie peut se faire à différents niveaux d’abstraction.

8 Temps d’exécution (fréquence) Consommation d’énergie (ou puissance) Surface en silicium (transistors) Coût Ces critères peuvent être estimés à différents niveaux d’abstraction Des outils académiques et industriels sont développés pour estimer chaque critère. Analyse multicritères du système

9 Adéquation Application/Architecture: –optimisation multi-objective –Trouver un ensemble de trade-offs: Temps, puissance, taille, coût…

10 Semiconductor Industry Roadmap

11 Evolution du nombre de transistor

12 Pentium® proc P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel Densité de Puissance

13 10,000 1, Logic transistors per chip (in millions) 100,000 10, Productivity (K) Trans./Staff-Mo IC capacity productivity Gap 1981 leading edge chip required 100 designer months 10,000 transistors / 100 transistors/month 2002 leading edge chip requires 30,000 designer months 150,000,000 / 5000 transistors/month Designer cost increase from $1M to $300M Nombre de transistors/Productivité

14 Puissance vs. Nombre de transistor taille des Tr en nm F en Ghz Prévisions ITRS 2003 année W W

15 Abstraction Level Objectives FunctionalApplication TLM Transaction Level Modeling Communicants Process (CP) Syst description.= comm process, Data exchange between functions. Programmer View (PV) Defined architecture. Functional verification. Communication with channels Cycle Accurate and/or Bit accurate Cycle Accurate*  Archi, pipeline, … Précis au bit (CABA)* Communication protocol. RTL : Register Transfer Level Implementation details: functional units, logic gates Accuracy Speed up Niveaux d’abstraction pour la simulation

16 Techniques d’estimation de performances Emulation: plateforme réelle existante Totalement reconfigurable/ Partiellement reconfigurable Exemple: plateforme FPGA, ALTERA, XILINX… Mesures directes des performances: temps d’exécution, consommation, surface... Simulation: plateforme non existante Description du système Différents niveaux: RTL (Register Transfer Level), CABA (Cycle Accurate Bit Accurate), TLM (Transaction Level Modeling) et Functional Level. Différents langages de description: VHDL, SystemC, Verilog…

17 Emulation Calcul d’énergie Calcul d’énergie Mesure de temps Mesure de temps A Analyse Programme asm ou C ou Reconfiguration (VHDL) Programme asm ou C ou Reconfiguration (VHDL)

18 SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G Niveaux d’implémentation d’un composant Accuracy Speed up

19 Reflect the actual circuit layout, include geometric information, cannot be simulated directly: behavior can be deduced by correlating the layout model with a behavioral description at a higher level or by extracting circuits from the layout. Length of wires and capacitances frequently extracted from the layout, back-annotated to descriptions at higher levels (more precision for delay and power estimations). Reflect the actual circuit layout, include geometric information, cannot be simulated directly: behavior can be deduced by correlating the layout model with a behavioral description at a higher level or by extracting circuits from the layout. Length of wires and capacitances frequently extracted from the layout, back-annotated to descriptions at higher levels (more precision for delay and power estimations). Simulation au niveau physique

20 din powlo powhi dout © Mosis (http://www. mosis.org/Technical/ Designsupport/ polyflowC.html); Tool: Cadence Simulation au niveau physique: exemple

21 Simulation au niveau transistor using analog simulator (SPICE) Input: Models (transistor, gates, macro) Textual netlist (schematic, extracted layout, behavioral) Output:Circuit response (waveforms, patterns) Time domain Frequency domain Power analysis

22 Simulation au niveau transistor: exemple

23 Simulation au niveau porte logic Models contain gates as the basic components. Provide accurate information about signal transition probabilities and can therefore also be used for power estimations. Delay calculations can be more precise than for the RTL. Typically no information about the length of wires (still estimates). Term sometimes also employed to denote Boolean functions (No physical gates; only considering the behavior of the gates). Such models should be called “Boolean function models”. Models contain gates as the basic components. Provide accurate information about signal transition probabilities and can therefore also be used for power estimations. Delay calculations can be more precise than for the RTL. Typically no information about the length of wires (still estimates). Term sometimes also employed to denote Boolean functions (No physical gates; only considering the behavior of the gates). Such models should be called “Boolean function models”.

24 Simulation au niveau porte logic: Exemple source: seul.org/ screenshots/ screenshot- schem2.png

25 At this level, we model all the components at the register- transfer level, including arithmetic/logic units (ALUs), registers, memories, muxes and decoders. Models at this level are always cycle-true. Automatic synthesis from such models is not a major challenge. At this level, we model all the components at the register- transfer level, including arithmetic/logic units (ALUs), registers, memories, muxes and decoders. Models at this level are always cycle-true. Automatic synthesis from such models is not a major challenge. Simulation au niveau RTL

26 Simulation au niveau RTL: exemple Controller B PCPC Instruction register IR Memor y Speich er alu_ contro l T sign_ extend << 2 4 * AL U Re g § 31:26 25:21 20:16 25:0 15:0 15:11 i2 a2 a1 i3 a3 a2 a1 o2 o1 PCSourc e TargetWrit e ALUOp ALUSel A ALUSel B RegWrit e RegDes t MemToReg IRWrite MemRead MemWrite PCWrite PCWriteC Ior D * § 31: 28 "00“


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