Patrice Quinton Séminaire COSI

Présentation au sujet: "Patrice Quinton Séminaire COSI"— Transcription de la présentation:

1 Patrice Quinton Séminaire COSI
Alpha : état des lieux Patrice Quinton Séminaire COSI Je vais présenter une synthèse des recherches que j ’ai effectuées à l ’Irisa en tant que chargé de recherche INRIA dans le projet API puis COSI. Ces recherches concernent la compilation de nids de boucles sur silicium. Patrice Quinton, Tanguy Risset 5/13/2019

2 Design flow with MMAlpha
VHDL FPGA ASIC Uniformization Scheduling RTL Derivation Patrice Quinton, Tanguy Risset 5/13/2019

3 Patrice Quinton, Tanguy Risset
Input should be C! Alpha VHDL FPGA ASIC Uniformization Scheduling RTL Derivation Patrice Quinton, Tanguy Risset 5/13/2019

4 Patrice Quinton, Tanguy Risset
OK! Input is C Alpha VHDL FPGA ASIC Uniformization Scheduling C RTL Derivation Patrice Quinton, Tanguy Risset 5/13/2019

5 Patrice Quinton, Tanguy Risset
Hide Alpha! Alpha VHDL FPGA ASIC Uniformization Scheduling C RTL Derivation Patrice Quinton, Tanguy Risset 5/13/2019

6 Patrice Quinton, Tanguy Risset
OK! Alpha is inside Alpha VHDL FPGA ASIC Uniformization Scheduling C RTL Derivation Patrice Quinton, Tanguy Risset 5/13/2019

7 Make uniformization automatic
Alpha VHDL FPGA ASIC Uniformization Scheduling C RTL Derivation Patrice Quinton, Tanguy Risset 5/13/2019

8 Patrice Quinton, Tanguy Risset
OK! It is automatic. Alpha VHDL FPGA ASIC Uniformization Scheduling C RTL Derivation Patrice Quinton, Tanguy Risset 5/13/2019

9 Scheduling is too complicated!
Alpha VHDL FPGA ASIC Uniformization Scheduling C RTL Derivation Patrice Quinton, Tanguy Risset 5/13/2019

10 OK. Now scheduling is easy.
Alpha VHDL FPGA ASIC Uniformization RTL Derivation C Patrice Quinton, Tanguy Risset 5/13/2019

11 Using Mathematica is a funny idea!
Alpha VHDL FPGA ASIC Uniformization RTL Derivation C Patrice Quinton, Tanguy Risset 5/13/2019

12 OK. Let’s recode MMAlpha in C++
VHDL FPGA ASIC Uniformization RTL Derivation C C++ Patrice Quinton, Tanguy Risset 5/13/2019

13 By the way, what does MMAlpha mean?
VHDL FPGA ASIC Uniformization RTL Derivation C C++ Patrice Quinton, Tanguy Risset 5/13/2019

14 Oups! Sorry for the mistake.
Alpha VHDL C2Vhdl FPGA ASIC Uniformization RTL Derivation C C++ Patrice Quinton, Tanguy Risset 5/13/2019

15 Patrice Quinton, Tanguy Risset
Oups! I forgot this… Alpha VHDL C2Vhdl FPGA ASIC Alpha inside Uniformization RTL Derivation C C++ Patrice Quinton, Tanguy Risset 5/13/2019

16 Franchement, on se demande à quoi sert la recherche!
Patrice Quinton, Tanguy Risset 5/13/2019

17 Patrice Quinton, Tanguy Risset
Les exposés à venir Scanning a union of polyedra (Gautam Gupta) 2D tiling (Aditya Gupta) Polylib (Rahul Tripathi) Interprétation hardware du temps multi-dimensionnel (Anne-Claire Guillou) Code generator of Alpha (Inderaj Bains) Patrice Quinton, Tanguy Risset 5/13/2019

18 Patrice Quinton, Tanguy Risset
Les exposés à venir Vérification pour Alpha (David Cachera) Méthodes formelles et modèle polyédrique (Katell Morin-Allory) Largeur des chemins de données (David Cachera et Tanguy Risset) Patrice Quinton, Tanguy Risset 5/13/2019